D-Flip Flop

Flip flops are the basic building blocks of a sequential logic circuit. They are devices that use a clock input signal. Each flip flop can store one bit.

What is a clock?

Clock_Signal

It is a signal that toggles between 0 and 1 repeatedly. The clock has 2 edges: The Rising Edge and the Falling Edge.

The image below shows the symbol of a flip flop:

D_FF

A D-Flip Flop copies the signal at the data input (D) to the output (Q) when there is a rising edge on the clock input (clk).

The Verilog and VHDL representations of a D-Flip Flop are as shown below:

D_FF_VERILOG_VHDL

Keyword: posedge – posedge (positive edge) specifies the direction of the clock (clk) signal changing towards 1. The rising edge is expressed by the posedge clk event in the sensitivity list.

The 2 Types of Resets:

The primary purpose of a reset is to force the design into a known state for stable operations. A good design guideline is to provide reset to every flip-flop in a system on chip (SoC). A design may choose to use either an Asynchronous or Synchronous reset or a mix of two.

D FF with asynchronous reset:

The reset signal clears the D FF to 0 at any time and is not controlled by the clock signal. Note that the posedge rst (reset signal) is included in the sensitivity list and its value is checked first in the if statement.

D FF with synchronous reset:

The synchronous reset signal will only affect or reset the state of the flip flop on the active edge of the clock. Note that the posedge rst (reset signal) is not included in the sensitivity list.

Given below are the verilog representations:

D_FF_ASYNC_SYNC

To get to know more about Asynchronous or Synchronous resets check out the link below:

Synchronous & Asynchronous Reset: http://vlsi.pro/synchronous-asynchronous-reset/

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